1. Field
The disclosed embodiments generally relate to the design of memory systems for computers. More specifically, the disclosed embodiments relate to the design of a multi-modal memory interface that supports both current-mode and voltage-mode signaling.
2. Related Art
Memory systems are beginning to use differential signaling techniques to achieve higher performance and better power efficiency than can be achieved through using conventional single-ended signaling techniques. In order to provide a smooth transition path toward memory systems that use differential signaling, it is advantageous to provide multi-modal memory controllers which are able to support both types of signaling. In this way, processor manufacturers can produce a single processor chip (and associated chip package) to provide a memory controller that can be used with memory devices that support either differential or single-ended signaling.
However, because of the incompatible voltage and swing levels for standard single-ended memories (>1.2V supply and >600 mV swing) and high-end differential memories (<1.2V supply and <600 mV swing), a multi-modal memory controller often must connect at least two different I/O drivers to the same I/O pad. Unfortunately, this creates additional capacitance, which can adversely affect high-speed signaling performance. Hence, it is desirable to be able to minimize the amount of capacitance associated with an I/O pad that is coupled to multiple I/O drivers.